module top (
    input clk,
    input rst,
    input [15:0] sw,
    input ps2_clk,
    input ps2_data,
    input [4:0] button,
    output [15:0] ledr,
    output VGA_CLK,
    output VGA_HSYNC,
    output VGA_VSYNC,
    output VGA_BLANK_N,
    output [7:0] VGA_R,
    output [7:0] VGA_G,
    output [7:0] VGA_B,
    output [7:0] seg0,
    output [7:0] seg1,
    output [7:0] seg2,
    output [7:0] seg3,
    output [7:0] seg4,
    output [7:0] seg5,
    output [7:0] seg6,
    output [7:0] seg7
);
wire [3:0] addr;
wire [7:0] ins;
wire [7:0] out_rs;

// sCPU
sCPU scpu(
    .clk(clk),
    .reset(rst),
    .ins(ins),
    .pc(addr),
    .out_rs(out_rs)
);
// 磁盘
ram ram1(
    .addr(addr),
    .data(ins)
);
// CPU和外设连接
bcd7seg bcd7seg_0(
  .b(out_rs[3:0]),
  .en(1'b1),
  .h(seg0[7:1])
);
bcd7seg bcd7seg_1(
  .b(out_rs[7:4]),
  .en(1'b1),
  .h(seg1[7:1])
);
/*
// 显存
vmem my_vmem(
    .addr(addr),
    .data(data),
    .h_addr(h_addr),
    .v_addr(v_addr[8:0]),
    .vga_data(vga_data)
);
// VGA显示
assign VGA_CLK = clk;

wire [23:0] vga_data;

vga_ctrl my_vga_ctrl(
    .pclk(clk),
    .reset(rst),
    .vga_data(vga_data),
    .h_addr(h_addr),
    .v_addr(v_addr),
    .hsync(VGA_HSYNC),
    .vsync(VGA_VSYNC),
    .valid(VGA_BLANK_N),
    .vga_r(VGA_R),
    .vga_g(VGA_G),
    .vga_b(VGA_B)
);
*/
endmodule

module vmem (
    input [18:0] addr,
    input [23:0] data,
    input w_en,
    input [9:0] h_addr,
    input [8:0] v_addr,
    output [23:0] vga_data
);

reg [23:0] vga_mem [524287:0];

assign vga_data = vga_mem[{h_addr, v_addr}];
assign vga_mem[addr] = w_en? data: vga_mem[addr];

endmodule

module ram #(BIT=4, WIDTH=8) (
    input [(BIT-1):0] addr,
    output [(WIDTH-1):0] data
);
    //连续的内存块
    reg [(WIDTH-1):0] ram[((1<<BIT)-1):0];

initial begin
    $readmemh("resource/add10.hex", ram);
end
    assign data = ram[addr];
endmodule

